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Outrush Reactor Transient Recovery Voltage Studies

Background

Current limiting outrush reactors (see figure below) are often installed with utility transmission capacitor banks. These reactors limit the high-magnitude, high-frequency currents that flow when the capacitor bank discharges into a nearby fault. While an outrush reactor reduces the magnitude and frequency of the current during close-in faults, it may cause excessive transient recovery voltages (TRVs) for the capacitor bank circuit breaker due to the very high frequency component of the recovery voltage associated with the natural frequency of the reactor. Excessive TRVs may cause a capacitor bank circuit breaker failure to clear during certain fault conditions. An engineering study can be completed to evaluate the TRVs for various capacitor bank circuit breaker operations, system contingencies, and mitigation alternatives.

The analysis of high-frequency TRVs frequently requires the use of sophisticated digital simulation tools. Simulations provide a convenient means to characterize transient events, determine resulting problems, and evaluate possible mitigation alternatives. Occasionally, they are performed in conjunction with system monitoring for verification of models and identification of important power system problems. The complexity of the models required for the simulations generally depends on the system characteristics and the transient phenomena under investigation.

Electrotek utilizes the PSCAD® program for TRV analysis. This program can be used for the analysis of circuit switching operations, capacitor bank switching, lightning transients, and transients associated with the operation of power electronic equipment. The output from each simulation case is plotted against the circuit breaker's withstand capability using routines developed in MATLAB® (examples shown below).

The goals for the study are to first determine if the TRV waveshapes exceed their related capability limits and then to evaluate the effectiveness of adding capacitance between the reactor and circuit breaker to reduce the TRV to within the related capabilities.

Study Methodology

The TRV evaluation for various fault conditions is based on the methods provided in IEEE Std. C37.06, IEEE Std. C37.04, and IEEE Std. C37.011. This involves analysis of the most severe conditions, including the clearing of three-phase and single-line-to-ground faults at the capacitor bank circuit breaker and outrush reactor terminals when the system voltage is at a maximum.

The study includes normal cases where the system operates with all circuit breakers and lines in service and various contingencies representing different operating conditions. For each case, three-phase ungrounded, three-phase grounded, and single-line-to-ground faults are evaluated.

For cases where the simulated TRV exceeds the withstand capability of the circuit breaker, the mitigation option of added capacitance is also evaluated.

Model Development and Verification

The simulation model development process includes steps for data collection, data approximation, data simplification, and model verification.

The TRV system model is based on short-circuit data that consists of positive and zero sequence impedances. The study area includes the substation and the adjacent system. All transmission lines are represented with a frequency dependent line model to account for traveling wave phenomena. The boundary of the study area is represented with equivalent sources and transfer impedances such that the electrical representation of the study area at 60 Hz is nearly identical to the original system. The accuracy of the transient model is verified by comparing three-phase and single-line-to-ground fault currents at all of the buses. The extent of the simulation model is determined during the initial stage of the study.

Portion of the Outrush Reactor TRV Evaluation Model
Portion of the Outrush Reactor TRV Evaluation Model

Simulation Results

The TRV evaluation includes both three-phase and single-line-to-ground faults at the outrush reactor terminals. The figure below shows an example simulation result illustrating the recovery voltage for a single-line-to-ground fault at the terminal of the outrush reactor. The graph includes the simulated TRV using PSCAD and an overlay of the withstand capability of the circuit breaker based on the IEEE standards.

Circuit Breaker TRV without Added Capacitance
Circuit Breaker TRV without Added Capacitance

Simulation cases are completed to evaluate resulting TRVs for the capacitor bank circuit breaker when clearing faults at the outrush reactor terminal under normal conditions with additional capacitances (standard manufacturer ratings) added at the reactor terminals. The figure below shows an example simulation result illustrating the recovery voltage for a single-line-to-ground fault at the terminal of the outrush reactor with a capacitance (e.g., 5,000pF) added to the model.

Circuit Breaker TRV with Added Capacitance
Circuit Breaker TRV with Added Capacitance

Electrotek's capacitor bank outrush reactor TRV study includes an evaluation of circuit breaker performance during the clearing of both three-phase and single-line-to-ground faults at the circuit breaker and outrush reactor terminals. The study considers normal cases where the system operates with all breakers and lines in service, various contingency cases (e.g., line or transformer out of service), and various mitigation alternatives (e.g. added capacitance).


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